MIPS Instruction Reference

How to read this guide

d / s / t denote general-purpose registers; fd / fs / ft denote floating-point registers. imm is an immediate constant; label is a symbolic target. Most three-operand instructions put the destination first. Stores and branches need to be read separately.

Real instructions normally correspond to one machine instruction. Pseudo-instructions expand into one or more real instructions. Classification applies to the exact operand form shown: conveniences such as add $t0,$t1,10 or lw $t0,label are extended forms. mul is real in classic MIPS32 but may be a pseudo-instruction on earlier targets.

This guide covers common integer, memory, control-flow and basic floating-point operations. It does not enumerate privileged instructions, atomics, DSP, MSA or every ISA revision. MIPS32 Release 6 changes multiplication, division and control flow, among other features. Instruction and expansion references: MARS basic-instruction implementation; MARS pseudo-instruction expansion table.

Registers: bits first, interpretation second

The 32 general-purpose registers each hold 32 bits. They have no inherent signed, unsigned or pointer type; an instruction determines how to interpret the bits.

The register number is the 5-bit value placed in an instruction's register field, not the value stored in the register. For example, $t0 = register 8 = 01000 in binary (0x08). Names and numbers in each grouped row correspond in order: $t0 = 8 (01000), $t1 = 9 (01001), …, $t7 = 15 (01111). You can also write $8 instead of $t0 in assembly.

Name	Register number (decimal)	Register number (5-bit binary)	Register number (hexadecimal)	Usage
`$zero / $0`	`0`	`00000`	`0x00`	The constant value 0; writes are discarded.
`$at`	`1`	`00001`	`0x01`	Assembler temporary.
`$v0–$v1`	`2–3`	`00010–00011`	`0x02–0x03`	Procedure return values; MARS also uses $v0 for syscall service numbers.
`$a0–$a3`	`4–7`	`00100–00111`	`0x04–0x07`	Procedure arguments.
`$t0–$t7`	`8–15`	`01000–01111`	`0x08–0x0F`	Temporaries; caller-saved.
`$s0–$s7`	`16–23`	`10000–10111`	`0x10–0x17`	Saved variables; callee-saved.
`$t8–$t9`	`24–25`	`11000–11001`	`0x18–0x19`	More temporaries; caller-saved.
`$k0–$k1`	`26–27`	`11010–11011`	`0x1A–0x1B`	OS temporaries; reserved for kernel or exception-handler use.
`$gp`	`28`	`11100`	`0x1C`	Global pointer.
`$sp`	`29`	`11101`	`0x1D`	Stack pointer.
`$fp / $s8`	`30`	`11110`	`0x1E`	Frame pointer, or another saved register.
`$ra`	`31`	`11111`	`0x1F`	Procedure return address.

$fp and $s8 are two names for the same register: 30 = 11110 in binary (0x1E).

HI, LO and PC are separate special registers. They do not have general-purpose register numbers 0–31 and cannot be selected through an ordinary 5-bit rs, rt or rd field.

Most register roles are calling conventions, not hardware restrictions. See UNSW 2026 MIPS instruction reference.

Integer arithmetic

Instruction	Syntax, meaning and example
add # Real	`add d, s, t` Add signed integers; raise an exception on signed overflow. `add $t0, $t1, $t2` R format · opcode 0 (0x00) · funct 32 (0x20) opcode [6]`000000`0 (0x00)rs [5]`s`rt [5]`t`rd [5]`d`shamt [5]`00000`0 (0x00)funct [6]`100000`32 (0x20) Fields run from bit 31 on the left to bit 0 on the right. Brackets show widths. Field values use decimal followed by hexadecimal, alongside the binary bits. Immediate fields show their unsigned raw bits; signed interpretation depends on the instruction. Register fields contain 5-bit register numbers. Unused fields shown as zero must be zero in this form. Example word: `19546144 (0x012A4020)` 0000 0001 0010 1010 0100 0000 0010 0000 Encoding checked against pinned MARS ac3d34ea65c3.
addu # Real	`addu d, s, t` Add and keep the low 32 bits; no overflow exception. `addu $t0, $t1, $t2` R format · opcode 0 (0x00) · funct 33 (0x21) opcode [6]`000000`0 (0x00)rs [5]`s`rt [5]`t`rd [5]`d`shamt [5]`00000`0 (0x00)funct [6]`100001`33 (0x21) Fields run from bit 31 on the left to bit 0 on the right. Brackets show widths. Field values use decimal followed by hexadecimal, alongside the binary bits. Immediate fields show their unsigned raw bits; signed interpretation depends on the instruction. Register fields contain 5-bit register numbers. Unused fields shown as zero must be zero in this form. Example word: `19546145 (0x012A4021)` 0000 0001 0010 1010 0100 0000 0010 0001 Encoding checked against pinned MARS ac3d34ea65c3.
addi # Real	`addi t, s, imm` Add a sign-extended 16-bit immediate; trap on signed overflow. `addi $t0, $t1, -1` I format · opcode 8 (0x08) · no funct opcode [6]`001000`8 (0x08)rs [5]`s`rt [5]`t`immediate [16]`imm` Fields run from bit 31 on the left to bit 0 on the right. Brackets show widths. Field values use decimal followed by hexadecimal, alongside the binary bits. Immediate fields show their unsigned raw bits; signed interpretation depends on the instruction. The immediate is sign-extended, including for sltiu. Example word: `556335103 (0x2128FFFF)` 0010 0001 0010 1000 1111 1111 1111 1111 Encoding checked against pinned MARS ac3d34ea65c3.
addiu # Real	`addiu t, s, imm` The immediate is still sign-extended; no overflow exception. `addiu $sp, $sp, -16` I format · opcode 9 (0x09) · no funct opcode [6]`001001`9 (0x09)rs [5]`s`rt [5]`t`immediate [16]`imm` Fields run from bit 31 on the left to bit 0 on the right. Brackets show widths. Field values use decimal followed by hexadecimal, alongside the binary bits. Immediate fields show their unsigned raw bits; signed interpretation depends on the instruction. The immediate is sign-extended, including for sltiu. Example word: `666763248 (0x27BDFFF0)` 0010 0111 1011 1101 1111 1111 1111 0000 Encoding checked against pinned MARS ac3d34ea65c3.
sub # Real	`sub d, s, t` Subtract t from s; trap on signed overflow. `sub $t0, $t1, $t2` R format · opcode 0 (0x00) · funct 34 (0x22) opcode [6]`000000`0 (0x00)rs [5]`s`rt [5]`t`rd [5]`d`shamt [5]`00000`0 (0x00)funct [6]`100010`34 (0x22) Fields run from bit 31 on the left to bit 0 on the right. Brackets show widths. Field values use decimal followed by hexadecimal, alongside the binary bits. Immediate fields show their unsigned raw bits; signed interpretation depends on the instruction. Register fields contain 5-bit register numbers. Unused fields shown as zero must be zero in this form. Example word: `19546146 (0x012A4022)` 0000 0001 0010 1010 0100 0000 0010 0010 Encoding checked against pinned MARS ac3d34ea65c3.
subu # Real	`subu d, s, t` Subtract and keep the low 32 bits; no overflow exception. `subu $t0, $t1, $t2` R format · opcode 0 (0x00) · funct 35 (0x23) opcode [6]`000000`0 (0x00)rs [5]`s`rt [5]`t`rd [5]`d`shamt [5]`00000`0 (0x00)funct [6]`100011`35 (0x23) Fields run from bit 31 on the left to bit 0 on the right. Brackets show widths. Field values use decimal followed by hexadecimal, alongside the binary bits. Immediate fields show their unsigned raw bits; signed interpretation depends on the instruction. Register fields contain 5-bit register numbers. Unused fields shown as zero must be zero in this form. Example word: `19546147 (0x012A4023)` 0000 0001 0010 1010 0100 0000 0010 0011 Encoding checked against pinned MARS ac3d34ea65c3.
mul # Real	`mul d, s, t` A real instruction in classic MIPS32: keep the low 32 product bits. Do not rely on HI/LO afterward. Earlier targets may implement it as a pseudo-instruction. `mul $t0, $t1, $t2` SPECIAL2 / R format · opcode 28 (0x1C) · funct 2 (0x02) opcode [6]`011100`28 (0x1C)rs [5]`s`rt [5]`t`rd [5]`d`shamt [5]`00000`0 (0x00)funct [6]`000010`2 (0x02) Fields run from bit 31 on the left to bit 0 on the right. Brackets show widths. Field values use decimal followed by hexadecimal, alongside the binary bits. Immediate fields show their unsigned raw bits; signed interpretation depends on the instruction. Register fields contain 5-bit register numbers. Unused fields shown as zero must be zero in this form. Example word: `1898594306 (0x712A4002)` 0111 0001 0010 1010 0100 0000 0000 0010 Encoding checked against pinned MARS ac3d34ea65c3.
mult # Real	`mult s, t` Multiply two signed 32-bit integers. Write the signed 64-bit product to HI:LO. `mult $t1, $t2` R format · opcode 0 (0x00) · funct 24 (0x18) opcode [6]`000000`0 (0x00)rs [5]`s`rt [5]`t`rd [5]`00000`0 (0x00)shamt [5]`00000`0 (0x00)funct [6]`011000`24 (0x18) Fields run from bit 31 on the left to bit 0 on the right. Brackets show widths. Field values use decimal followed by hexadecimal, alongside the binary bits. Immediate fields show their unsigned raw bits; signed interpretation depends on the instruction. Register fields contain 5-bit register numbers. Unused fields shown as zero must be zero in this form. Example word: `19529752 (0x012A0018)` 0000 0001 0010 1010 0000 0000 0001 1000 Encoding checked against pinned MARS ac3d34ea65c3.
multu # Real	`multu s, t` Multiply two unsigned 32-bit integers. Write the unsigned 64-bit product to HI:LO. `multu $t1, $t2` R format · opcode 0 (0x00) · funct 25 (0x19) opcode [6]`000000`0 (0x00)rs [5]`s`rt [5]`t`rd [5]`00000`0 (0x00)shamt [5]`00000`0 (0x00)funct [6]`011001`25 (0x19) Fields run from bit 31 on the left to bit 0 on the right. Brackets show widths. Field values use decimal followed by hexadecimal, alongside the binary bits. Immediate fields show their unsigned raw bits; signed interpretation depends on the instruction. Register fields contain 5-bit register numbers. Unused fields shown as zero must be zero in this form. Example word: `19529753 (0x012A0019)` 0000 0001 0010 1010 0000 0000 0001 1001 Encoding checked against pinned MARS ac3d34ea65c3.
div # Real	`div s, t` Divide signed s by signed t. LO receives the quotient, truncated toward zero; HI receives the remainder. Check division by zero and INT_MIN / -1 first. `div $t1, $t2` R format · opcode 0 (0x00) · funct 26 (0x1A) opcode [6]`000000`0 (0x00)rs [5]`s`rt [5]`t`rd [5]`00000`0 (0x00)shamt [5]`00000`0 (0x00)funct [6]`011010`26 (0x1A) Fields run from bit 31 on the left to bit 0 on the right. Brackets show widths. Field values use decimal followed by hexadecimal, alongside the binary bits. Immediate fields show their unsigned raw bits; signed interpretation depends on the instruction. Register fields contain 5-bit register numbers. Unused fields shown as zero must be zero in this form. Example word: `19529754 (0x012A001A)` 0000 0001 0010 1010 0000 0000 0001 1010 Encoding checked against pinned MARS ac3d34ea65c3.
divu # Real	`divu s, t` Divide unsigned s by unsigned t. LO receives the quotient; HI receives the remainder. Check division by zero first. `divu $t1, $t2` R format · opcode 0 (0x00) · funct 27 (0x1B) opcode [6]`000000`0 (0x00)rs [5]`s`rt [5]`t`rd [5]`00000`0 (0x00)shamt [5]`00000`0 (0x00)funct [6]`011011`27 (0x1B) Fields run from bit 31 on the left to bit 0 on the right. Brackets show widths. Field values use decimal followed by hexadecimal, alongside the binary bits. Immediate fields show their unsigned raw bits; signed interpretation depends on the instruction. Register fields contain 5-bit register numbers. Unused fields shown as zero must be zero in this form. Example word: `19529755 (0x012A001B)` 0000 0001 0010 1010 0000 0000 0001 1011 Encoding checked against pinned MARS ac3d34ea65c3.
mfhi # Real	`mfhi d` Copy the contents of HI into general-purpose register d; use this to retrieve a division remainder or the high half of a multiplication result. `mfhi $t0` R format · opcode 0 (0x00) · funct 16 (0x10) opcode [6]`000000`0 (0x00)rs [5]`00000`0 (0x00)rt [5]`00000`0 (0x00)rd [5]`d`shamt [5]`00000`0 (0x00)funct [6]`010000`16 (0x10) Fields run from bit 31 on the left to bit 0 on the right. Brackets show widths. Field values use decimal followed by hexadecimal, alongside the binary bits. Immediate fields show their unsigned raw bits; signed interpretation depends on the instruction. Register fields contain 5-bit register numbers. Unused fields shown as zero must be zero in this form. Example word: `16400 (0x00004010)` 0000 0000 0000 0000 0100 0000 0001 0000 Encoding checked against pinned MARS ac3d34ea65c3.
mflo # Real	`mflo d` Copy the contents of LO into general-purpose register d; use this to retrieve a division quotient or the low half of a multiplication result. `mflo $t0` R format · opcode 0 (0x00) · funct 18 (0x12) opcode [6]`000000`0 (0x00)rs [5]`00000`0 (0x00)rt [5]`00000`0 (0x00)rd [5]`d`shamt [5]`00000`0 (0x00)funct [6]`010010`18 (0x12) Fields run from bit 31 on the left to bit 0 on the right. Brackets show widths. Field values use decimal followed by hexadecimal, alongside the binary bits. Immediate fields show their unsigned raw bits; signed interpretation depends on the instruction. Register fields contain 5-bit register numbers. Unused fields shown as zero must be zero in this form. Example word: `16402 (0x00004012)` 0000 0000 0000 0000 0100 0000 0001 0010 Encoding checked against pinned MARS ac3d34ea65c3.
mthi # Real	`mthi s` Copy general-purpose register s into HI. LO is unchanged. `mthi $t0` R format · opcode 0 (0x00) · funct 17 (0x11) opcode [6]`000000`0 (0x00)rs [5]`s`rt [5]`00000`0 (0x00)rd [5]`00000`0 (0x00)shamt [5]`00000`0 (0x00)funct [6]`010001`17 (0x11) Fields run from bit 31 on the left to bit 0 on the right. Brackets show widths. Field values use decimal followed by hexadecimal, alongside the binary bits. Immediate fields show their unsigned raw bits; signed interpretation depends on the instruction. Register fields contain 5-bit register numbers. Unused fields shown as zero must be zero in this form. Example word: `16777233 (0x01000011)` 0000 0001 0000 0000 0000 0000 0001 0001 Encoding checked against pinned MARS ac3d34ea65c3.
mtlo # Real	`mtlo s` Copy general-purpose register s into LO. HI is unchanged. `mtlo $t0` R format · opcode 0 (0x00) · funct 19 (0x13) opcode [6]`000000`0 (0x00)rs [5]`s`rt [5]`00000`0 (0x00)rd [5]`00000`0 (0x00)shamt [5]`00000`0 (0x00)funct [6]`010011`19 (0x13) Fields run from bit 31 on the left to bit 0 on the right. Brackets show widths. Field values use decimal followed by hexadecimal, alongside the binary bits. Immediate fields show their unsigned raw bits; signed interpretation depends on the instruction. Register fields contain 5-bit register numbers. Unused fields shown as zero must be zero in this form. Example word: `16777235 (0x01000013)` 0000 0001 0000 0000 0000 0000 0001 0011 Encoding checked against pinned MARS ac3d34ea65c3.
neg # Pseudo	`neg d, s` Compute d = 0 − s as a signed operation. Signed overflow raises an exception; negating INT_MIN cannot be represented. `neg $t0, $t1` Expansion · 1 real instructions · no opcode of its own Pinned MARS expansion for this operand form. sub d, $zero, s Symbolic operands d/s/t stand for registers. Click a real mnemonic above to see its encoding. neg $t1,$t2 is the source template form. ac3d34ea65c3.
negu # Pseudo	`negu d, s` Compute d = 0 − s modulo 2^32. No signed-overflow exception is raised. `negu $t0, $t1` Expansion · 1 real instructions · no opcode of its own Pinned MARS expansion for this operand form. subu d, $zero, s Symbolic operands d/s/t stand for registers. Click a real mnemonic above to see its encoding. negu $t1,$t2 is the source template form. ac3d34ea65c3.
abs # Pseudo	`abs d, s` Signed absolute value. The absolute value of INT_MIN is not representable as a signed 32-bit integer. `abs $t0, $t1` Expansion · 3 real instructions · no opcode of its own 3 real instructions. Clobbers $at. The pinned sequence returns INT_MIN unchanged for INT_MIN; it does not trap on that unrepresentable positive absolute value. sra $at, s, 31 xor d, $at, s subu d, d, $at Symbolic operands d/s/t stand for registers. Click a real mnemonic above to see its encoding. abs $t1,$t2 is the source template form. ac3d34ea65c3.
rem # Pseudo	`rem d, s, t` Compute the signed remainder s % t. Commonly expands to signed division and a read of HI. Check division boundaries first. `rem $t0, $t1, $t2` Expansion · 4–5 real instructions · no opcode of its own Pinned MARS inserts a divisor-zero guard. With delayed branching enabled, insert nop immediately after bne; the internal target still resolves to the divide instruction. Clobbers HI/LO. Signed overflow boundaries still need a caller check. The label here is explanatory and must be unique if used in source. bne t, $zero, do_divide # nop here only when delayed branching is enabled break do_divide: div s, t mfhi d Symbolic operands d/s/t stand for registers. Click a real mnemonic above to see its encoding. rem $t1,$t2,$t3 is the source template form. ac3d34ea65c3.
remu # Pseudo	`remu d, s, t` Compute the unsigned remainder s % t. Commonly expands to unsigned division and a read of HI. The divisor must be nonzero. `remu $t0, $t1, $t2` Expansion · 4–5 real instructions · no opcode of its own Pinned MARS inserts a divisor-zero guard. With delayed branching enabled, insert nop immediately after bne; the internal target still resolves to the divide instruction. Clobbers HI/LO. Signed overflow boundaries still need a caller check. The label here is explanatory and must be unique if used in source. bne t, $zero, do_divide # nop here only when delayed branching is enabled break do_divide: divu s, t mfhi d Symbolic operands d/s/t stand for registers. Click a real mnemonic above to see its encoding. remu $t1,$t2,$t3 is the source template form. ac3d34ea65c3.

Bitwise operations and shifts

Instruction	Syntax, meaning and example
and # Real	`and d, s, t` Bitwise AND: each result bit is 1 only when both corresponding operand bits are 1. d = s AND t. `and $t0, $t1, $t2` R format · opcode 0 (0x00) · funct 36 (0x24) opcode [6]`000000`0 (0x00)rs [5]`s`rt [5]`t`rd [5]`d`shamt [5]`00000`0 (0x00)funct [6]`100100`36 (0x24) Fields run from bit 31 on the left to bit 0 on the right. Brackets show widths. Field values use decimal followed by hexadecimal, alongside the binary bits. Immediate fields show their unsigned raw bits; signed interpretation depends on the instruction. Register fields contain 5-bit register numbers. Unused fields shown as zero must be zero in this form. Example word: `19546148 (0x012A4024)` 0000 0001 0010 1010 0100 0000 0010 0100 Encoding checked against pinned MARS ac3d34ea65c3.
or # Real	`or d, s, t` Bitwise OR: each result bit is 1 when either corresponding operand bit is 1. d = s OR t. `or $t0, $t1, $t2` R format · opcode 0 (0x00) · funct 37 (0x25) opcode [6]`000000`0 (0x00)rs [5]`s`rt [5]`t`rd [5]`d`shamt [5]`00000`0 (0x00)funct [6]`100101`37 (0x25) Fields run from bit 31 on the left to bit 0 on the right. Brackets show widths. Field values use decimal followed by hexadecimal, alongside the binary bits. Immediate fields show their unsigned raw bits; signed interpretation depends on the instruction. Register fields contain 5-bit register numbers. Unused fields shown as zero must be zero in this form. Example word: `19546149 (0x012A4025)` 0000 0001 0010 1010 0100 0000 0010 0101 Encoding checked against pinned MARS ac3d34ea65c3.
xor # Real	`xor d, s, t` Bitwise exclusive OR: each result bit is 1 when the corresponding operand bits differ. d = s XOR t. `xor $t0, $t1, $t2` R format · opcode 0 (0x00) · funct 38 (0x26) opcode [6]`000000`0 (0x00)rs [5]`s`rt [5]`t`rd [5]`d`shamt [5]`00000`0 (0x00)funct [6]`100110`38 (0x26) Fields run from bit 31 on the left to bit 0 on the right. Brackets show widths. Field values use decimal followed by hexadecimal, alongside the binary bits. Immediate fields show their unsigned raw bits; signed interpretation depends on the instruction. Register fields contain 5-bit register numbers. Unused fields shown as zero must be zero in this form. Example word: `19546150 (0x012A4026)` 0000 0001 0010 1010 0100 0000 0010 0110 Encoding checked against pinned MARS ac3d34ea65c3.
nor # Real	`nor d, s, t` Compute ~(s OR t). `nor $t0, $t1, $zero` R format · opcode 0 (0x00) · funct 39 (0x27) opcode [6]`000000`0 (0x00)rs [5]`s`rt [5]`t`rd [5]`d`shamt [5]`00000`0 (0x00)funct [6]`100111`39 (0x27) Fields run from bit 31 on the left to bit 0 on the right. Brackets show widths. Field values use decimal followed by hexadecimal, alongside the binary bits. Immediate fields show their unsigned raw bits; signed interpretation depends on the instruction. Register fields contain 5-bit register numbers. Unused fields shown as zero must be zero in this form. Example word: `18890791 (0x01204027)` 0000 0001 0010 0000 0100 0000 0010 0111 Encoding checked against pinned MARS ac3d34ea65c3.
andi # Real	`andi t, s, imm` Zero-extend the 16-bit immediate, then compute t = s AND immediate. Useful for masking bits; immediate range 0…65535. `andi $t0, $t1, 0x00ff` I format · opcode 12 (0x0C) · no funct opcode [6]`001100`12 (0x0C)rs [5]`s`rt [5]`t`immediate [16]`imm` Fields run from bit 31 on the left to bit 0 on the right. Brackets show widths. Field values use decimal followed by hexadecimal, alongside the binary bits. Immediate fields show their unsigned raw bits; signed interpretation depends on the instruction. The immediate is a 16-bit unsigned field. Example word: `824705279 (0x312800FF)` 0011 0001 0010 1000 0000 0000 1111 1111 Encoding checked against pinned MARS ac3d34ea65c3.
ori # Real	`ori t, s, imm` Zero-extend the 16-bit immediate, then compute t = s OR immediate. Useful for setting bits; immediate range 0…65535. `ori $t0, $t1, 0x00ff` I format · opcode 13 (0x0D) · no funct opcode [6]`001101`13 (0x0D)rs [5]`s`rt [5]`t`immediate [16]`imm` Fields run from bit 31 on the left to bit 0 on the right. Brackets show widths. Field values use decimal followed by hexadecimal, alongside the binary bits. Immediate fields show their unsigned raw bits; signed interpretation depends on the instruction. The immediate is a 16-bit unsigned field. Example word: `891814143 (0x352800FF)` 0011 0101 0010 1000 0000 0000 1111 1111 Encoding checked against pinned MARS ac3d34ea65c3.
xori # Real	`xori t, s, imm` Zero-extend the 16-bit immediate, then compute t = s XOR immediate. Useful for toggling bits; immediate range 0…65535. `xori $t0, $t1, 0x00ff` I format · opcode 14 (0x0E) · no funct opcode [6]`001110`14 (0x0E)rs [5]`s`rt [5]`t`immediate [16]`imm` Fields run from bit 31 on the left to bit 0 on the right. Brackets show widths. Field values use decimal followed by hexadecimal, alongside the binary bits. Immediate fields show their unsigned raw bits; signed interpretation depends on the instruction. The immediate is a 16-bit unsigned field. Example word: `958923007 (0x392800FF)` 0011 1001 0010 1000 0000 0000 1111 1111 Encoding checked against pinned MARS ac3d34ea65c3.
lui # Real	`lui t, imm` Place the immediate in the upper 16 bits; clear the lower 16 bits. `lui $t0, 0x1234` I format · opcode 15 (0x0F) · no funct opcode [6]`001111`15 (0x0F)rs [5]`00000`0 (0x00)rt [5]`t`immediate [16]`imm` Fields run from bit 31 on the left to bit 0 on the right. Brackets show widths. Field values use decimal followed by hexadecimal, alongside the binary bits. Immediate fields show their unsigned raw bits; signed interpretation depends on the instruction. The immediate is a 16-bit unsigned field. Example word: `1007161908 (0x3C081234)` 0011 1100 0000 1000 0001 0010 0011 0100 Encoding checked against pinned MARS ac3d34ea65c3.
sll # Real	`sll d, t, shamt` Shift t left by shamt bits, fill low bits with zeroes and discard high bits. The immediate shift count is 0…31. `sll $t0, $t1, 3` R format · opcode 0 (0x00) · funct 0 (0x00) opcode [6]`000000`0 (0x00)rs [5]`00000`0 (0x00)rt [5]`t`rd [5]`d`shamt [5]`shamt`funct [6]`000000`0 (0x00) Fields run from bit 31 on the left to bit 0 on the right. Brackets show widths. Field values use decimal followed by hexadecimal, alongside the binary bits. Immediate fields show their unsigned raw bits; signed interpretation depends on the instruction. Register fields contain 5-bit register numbers. Unused fields shown as zero must be zero in this form. Example word: `606400 (0x000940C0)` 0000 0000 0000 1001 0100 0000 1100 0000 Encoding checked against pinned MARS ac3d34ea65c3.
srl # Real	`srl d, t, shamt` Shift t right logically by shamt bits, filling high bits with zeroes. The immediate shift count is 0…31. `srl $t0, $t1, 3` R format · opcode 0 (0x00) · funct 2 (0x02) opcode [6]`000000`0 (0x00)rs [5]`00000`0 (0x00)rt [5]`t`rd [5]`d`shamt [5]`shamt`funct [6]`000010`2 (0x02) Fields run from bit 31 on the left to bit 0 on the right. Brackets show widths. Field values use decimal followed by hexadecimal, alongside the binary bits. Immediate fields show their unsigned raw bits; signed interpretation depends on the instruction. Register fields contain 5-bit register numbers. Unused fields shown as zero must be zero in this form. Example word: `606402 (0x000940C2)` 0000 0000 0000 1001 0100 0000 1100 0010 Encoding checked against pinned MARS ac3d34ea65c3.
sra # Real	`sra d, t, shamt` Shift t right arithmetically by shamt bits, replicating the sign bit. The immediate shift count is 0…31. `sra $t0, $t1, 3` R format · opcode 0 (0x00) · funct 3 (0x03) opcode [6]`000000`0 (0x00)rs [5]`00000`0 (0x00)rt [5]`t`rd [5]`d`shamt [5]`shamt`funct [6]`000011`3 (0x03) Fields run from bit 31 on the left to bit 0 on the right. Brackets show widths. Field values use decimal followed by hexadecimal, alongside the binary bits. Immediate fields show their unsigned raw bits; signed interpretation depends on the instruction. Register fields contain 5-bit register numbers. Unused fields shown as zero must be zero in this form. Example word: `606403 (0x000940C3)` 0000 0000 0000 1001 0100 0000 1100 0011 Encoding checked against pinned MARS ac3d34ea65c3.
sllv # Real	`sllv d, t, s` Shift t left by the count in the low 5 bits of s. Fill low bits with zeroes; discard high bits. Operand order is destination, value, count. `sllv $t0, $t1, $t2` R format · opcode 0 (0x00) · funct 4 (0x04) opcode [6]`000000`0 (0x00)rs [5]`s`rt [5]`t`rd [5]`d`shamt [5]`00000`0 (0x00)funct [6]`000100`4 (0x04) Fields run from bit 31 on the left to bit 0 on the right. Brackets show widths. Field values use decimal followed by hexadecimal, alongside the binary bits. Immediate fields show their unsigned raw bits; signed interpretation depends on the instruction. Register fields contain 5-bit register numbers. Unused fields shown as zero must be zero in this form. Example word: `21577732 (0x01494004)` 0000 0001 0100 1001 0100 0000 0000 0100 Encoding checked against pinned MARS ac3d34ea65c3.
srlv # Real	`srlv d, t, s` Shift t right logically by the count in the low 5 bits of s. Fill high bits with zeroes. Operand order is destination, value, count. `srlv $t0, $t1, $t2` R format · opcode 0 (0x00) · funct 6 (0x06) opcode [6]`000000`0 (0x00)rs [5]`s`rt [5]`t`rd [5]`d`shamt [5]`00000`0 (0x00)funct [6]`000110`6 (0x06) Fields run from bit 31 on the left to bit 0 on the right. Brackets show widths. Field values use decimal followed by hexadecimal, alongside the binary bits. Immediate fields show their unsigned raw bits; signed interpretation depends on the instruction. Register fields contain 5-bit register numbers. Unused fields shown as zero must be zero in this form. Example word: `21577734 (0x01494006)` 0000 0001 0100 1001 0100 0000 0000 0110 Encoding checked against pinned MARS ac3d34ea65c3.
srav # Real	`srav d, t, s` Shift t right arithmetically by the count in the low 5 bits of s. Replicate the sign bit. Operand order is destination, value, count. `srav $t0, $t1, $t2` R format · opcode 0 (0x00) · funct 7 (0x07) opcode [6]`000000`0 (0x00)rs [5]`s`rt [5]`t`rd [5]`d`shamt [5]`00000`0 (0x00)funct [6]`000111`7 (0x07) Fields run from bit 31 on the left to bit 0 on the right. Brackets show widths. Field values use decimal followed by hexadecimal, alongside the binary bits. Immediate fields show their unsigned raw bits; signed interpretation depends on the instruction. Register fields contain 5-bit register numbers. Unused fields shown as zero must be zero in this form. Example word: `21577735 (0x01494007)` 0000 0001 0100 1001 0100 0000 0000 0111 Encoding checked against pinned MARS ac3d34ea65c3.
not # Pseudo	`not d, s` Invert every bit; commonly expands to nor d, s, $zero. `not $t0, $t1` Expansion · 1 real instructions · no opcode of its own Pinned MARS expansion for this operand form. nor d, s, $zero Symbolic operands d/s/t stand for registers. Click a real mnemonic above to see its encoding. not $t1,$t2 is the source template form. ac3d34ea65c3.

Comparisons and branches

Instruction	Syntax, meaning and example
slt # Real	`slt d, s, t` Compare s and t as signed 32-bit integers. Write 1 to d if s < t; otherwise write 0. `slt $t0, $t1, $t2` R format · opcode 0 (0x00) · funct 42 (0x2A) opcode [6]`000000`0 (0x00)rs [5]`s`rt [5]`t`rd [5]`d`shamt [5]`00000`0 (0x00)funct [6]`101010`42 (0x2A) Fields run from bit 31 on the left to bit 0 on the right. Brackets show widths. Field values use decimal followed by hexadecimal, alongside the binary bits. Immediate fields show their unsigned raw bits; signed interpretation depends on the instruction. Register fields contain 5-bit register numbers. Unused fields shown as zero must be zero in this form. Example word: `19546154 (0x012A402A)` 0000 0001 0010 1010 0100 0000 0010 1010 Encoding checked against pinned MARS ac3d34ea65c3.
sltu # Real	`sltu d, s, t` Compare s and t as unsigned 32-bit integers. Write 1 to d if s < t; otherwise write 0. `sltu $t0, $t1, $t2` R format · opcode 0 (0x00) · funct 43 (0x2B) opcode [6]`000000`0 (0x00)rs [5]`s`rt [5]`t`rd [5]`d`shamt [5]`00000`0 (0x00)funct [6]`101011`43 (0x2B) Fields run from bit 31 on the left to bit 0 on the right. Brackets show widths. Field values use decimal followed by hexadecimal, alongside the binary bits. Immediate fields show their unsigned raw bits; signed interpretation depends on the instruction. Register fields contain 5-bit register numbers. Unused fields shown as zero must be zero in this form. Example word: `19546155 (0x012A402B)` 0000 0001 0010 1010 0100 0000 0010 1011 Encoding checked against pinned MARS ac3d34ea65c3.
slti # Real	`slti t, s, imm` Sign-extend the 16-bit immediate, then compare it with signed s. Write 1 to t if s is less; otherwise write 0. `slti $t0, $t1, 10` I format · opcode 10 (0x0A) · no funct opcode [6]`001010`10 (0x0A)rs [5]`s`rt [5]`t`immediate [16]`imm` Fields run from bit 31 on the left to bit 0 on the right. Brackets show widths. Field values use decimal followed by hexadecimal, alongside the binary bits. Immediate fields show their unsigned raw bits; signed interpretation depends on the instruction. The immediate is sign-extended, including for sltiu. Example word: `690487306 (0x2928000A)` 0010 1001 0010 1000 0000 0000 0000 1010 Encoding checked against pinned MARS ac3d34ea65c3.
sltiu # Real	`sltiu t, s, imm` Sign-extend the 16-bit immediate, then interpret both operands as unsigned. Write 1 to t if s is less; otherwise write 0. The immediate is not zero-extended. `sltiu $t0, $t1, 10` I format · opcode 11 (0x0B) · no funct opcode [6]`001011`11 (0x0B)rs [5]`s`rt [5]`t`immediate [16]`imm` Fields run from bit 31 on the left to bit 0 on the right. Brackets show widths. Field values use decimal followed by hexadecimal, alongside the binary bits. Immediate fields show their unsigned raw bits; signed interpretation depends on the instruction. The immediate is sign-extended, including for sltiu. Example word: `757596170 (0x2D28000A)` 0010 1101 0010 1000 0000 0000 0000 1010 Encoding checked against pinned MARS ac3d34ea65c3.
beq # Real	`beq s, t, label` Branch to label if register s equals register t; otherwise continue. The real instruction compares two registers. `beq $t0, $t1, equal` I / branch format · opcode 4 (0x04) · no funct opcode [6]`000100`4 (0x04)rs [5]`s`rt [5]`t`offset [16]`branchOffset` Fields run from bit 31 on the left to bit 0 on the right. Brackets show widths. Field values use decimal followed by hexadecimal, alongside the binary bits. Immediate fields show their unsigned raw bits; signed interpretation depends on the instruction. offset = (target − (PC + 4)) / 4, signed 16 bits. Fixed rt bits select the condition where shown; there is no funct field. Example word: `285802503 (0x11090007)` 0001 0001 0000 1001 0000 0000 0000 0111 For this encoded example, assume PC = 0x00400000 and label = 0x00400020. The label in the example is illustrative. Encoding checked against pinned MARS ac3d34ea65c3.
bne # Real	`bne s, t, label` Branch to label if register s differs from register t; otherwise continue. The real instruction compares two registers. `bne $t0, $t1, different` I / branch format · opcode 5 (0x05) · no funct opcode [6]`000101`5 (0x05)rs [5]`s`rt [5]`t`offset [16]`branchOffset` Fields run from bit 31 on the left to bit 0 on the right. Brackets show widths. Field values use decimal followed by hexadecimal, alongside the binary bits. Immediate fields show their unsigned raw bits; signed interpretation depends on the instruction. offset = (target − (PC + 4)) / 4, signed 16 bits. Fixed rt bits select the condition where shown; there is no funct field. Example word: `352911367 (0x15090007)` 0001 0101 0000 1001 0000 0000 0000 0111 For this encoded example, assume PC = 0x00400000 and label = 0x00400020. The label in the example is illustrative. Encoding checked against pinned MARS ac3d34ea65c3.
bgez # Real	`bgez s, label` Branch to label if s, interpreted as a signed integer, is greater than or equal to zero. `bgez $t0, nonnegative` REGIMM / I format · opcode 1 (0x01) · no funct opcode [6]`000001`1 (0x01)rs [5]`s`rt [5]`00001`1 (0x01)offset [16]`branchOffset` Fields run from bit 31 on the left to bit 0 on the right. Brackets show widths. Field values use decimal followed by hexadecimal, alongside the binary bits. Immediate fields show their unsigned raw bits; signed interpretation depends on the instruction. offset = (target − (PC + 4)) / 4, signed 16 bits. Fixed rt bits select the condition where shown; there is no funct field. Example word: `83951623 (0x05010007)` 0000 0101 0000 0001 0000 0000 0000 0111 For this encoded example, assume PC = 0x00400000 and label = 0x00400020. The label in the example is illustrative. Encoding checked against pinned MARS ac3d34ea65c3.
bgtz # Real	`bgtz s, label` Branch to label if s, interpreted as a signed integer, is greater than zero. `bgtz $t0, positive` I / branch format · opcode 7 (0x07) · no funct opcode [6]`000111`7 (0x07)rs [5]`s`rt [5]`00000`0 (0x00)offset [16]`branchOffset` Fields run from bit 31 on the left to bit 0 on the right. Brackets show widths. Field values use decimal followed by hexadecimal, alongside the binary bits. Immediate fields show their unsigned raw bits; signed interpretation depends on the instruction. offset = (target − (PC + 4)) / 4, signed 16 bits. Fixed rt bits select the condition where shown; there is no funct field. Example word: `486539271 (0x1D000007)` 0001 1101 0000 0000 0000 0000 0000 0111 For this encoded example, assume PC = 0x00400000 and label = 0x00400020. The label in the example is illustrative. Encoding checked against pinned MARS ac3d34ea65c3.
blez # Real	`blez s, label` Branch to label if s, interpreted as a signed integer, is less than or equal to zero. `blez $t0, nonpositive` I / branch format · opcode 6 (0x06) · no funct opcode [6]`000110`6 (0x06)rs [5]`s`rt [5]`00000`0 (0x00)offset [16]`branchOffset` Fields run from bit 31 on the left to bit 0 on the right. Brackets show widths. Field values use decimal followed by hexadecimal, alongside the binary bits. Immediate fields show their unsigned raw bits; signed interpretation depends on the instruction. offset = (target − (PC + 4)) / 4, signed 16 bits. Fixed rt bits select the condition where shown; there is no funct field. Example word: `419430407 (0x19000007)` 0001 1001 0000 0000 0000 0000 0000 0111 For this encoded example, assume PC = 0x00400000 and label = 0x00400020. The label in the example is illustrative. Encoding checked against pinned MARS ac3d34ea65c3.
bltz # Real	`bltz s, label` Branch to label if s, interpreted as a signed integer, is less than zero. `bltz $t0, negative` REGIMM / I format · opcode 1 (0x01) · no funct opcode [6]`000001`1 (0x01)rs [5]`s`rt [5]`00000`0 (0x00)offset [16]`branchOffset` Fields run from bit 31 on the left to bit 0 on the right. Brackets show widths. Field values use decimal followed by hexadecimal, alongside the binary bits. Immediate fields show their unsigned raw bits; signed interpretation depends on the instruction. offset = (target − (PC + 4)) / 4, signed 16 bits. Fixed rt bits select the condition where shown; there is no funct field. Example word: `83886087 (0x05000007)` 0000 0101 0000 0000 0000 0000 0000 0111 For this encoded example, assume PC = 0x00400000 and label = 0x00400020. The label in the example is illustrative. Encoding checked against pinned MARS ac3d34ea65c3.
beqz # Pseudo	`beqz s, label` Branch to label if s is zero. Commonly expands to beq s, $zero, label. `beqz $t0, is_zero` Expansion · 1 real instructions · no opcode of its own Pinned MARS expansion for this operand form. The expansion ends in a real branch; its following instruction is the delay slot when delayed branching is enabled. MARS does not automatically append a nop for these ordinary branch pseudos. beq s, $zero, label Symbolic operands d/s/t stand for registers. Click a real mnemonic above to see its encoding. beqz $t1,label is the source template form. ac3d34ea65c3.
bnez # Pseudo	`bnez s, label` Branch to label if s is nonzero. Commonly expands to bne s, $zero, label. `bnez $t0, nonzero` Expansion · 1 real instructions · no opcode of its own Pinned MARS expansion for this operand form. The expansion ends in a real branch; its following instruction is the delay slot when delayed branching is enabled. MARS does not automatically append a nop for these ordinary branch pseudos. bne s, $zero, label Symbolic operands d/s/t stand for registers. Click a real mnemonic above to see its encoding. bnez $t1,label is the source template form. ac3d34ea65c3.
blt # Pseudo	`blt s, t, label` Branch to label if signed s < signed t. Commonly expands to a signed comparison followed by a conditional branch. `blt $t0, $t1, less` Expansion · 2 real instructions · no opcode of its own The expansion below follows the pinned MARS register-operand form. $at is register $1; reserve it for the assembler. The expansion ends in a real branch; its following instruction is the delay slot when delayed branching is enabled. MARS does not automatically append a nop for these ordinary branch pseudos. slt $at, s, t bne $at, $zero, label Symbolic operands d/s/t stand for registers. Click a real mnemonic above to see its encoding. blt $t1,$t2,label is the source template form. ac3d34ea65c3.
ble # Pseudo	`ble s, t, label` Branch to label if signed s ≤ signed t. Expands to a comparison and a conditional branch. `ble $t0, $t1, less_or_equal` Expansion · 2 real instructions · no opcode of its own The expansion below follows the pinned MARS register-operand form. $at is register $1; reserve it for the assembler. The expansion ends in a real branch; its following instruction is the delay slot when delayed branching is enabled. MARS does not automatically append a nop for these ordinary branch pseudos. slt $at, t, s beq $at, $zero, label Symbolic operands d/s/t stand for registers. Click a real mnemonic above to see its encoding. ble $t1,$t2,label is the source template form. ac3d34ea65c3.
bgt # Pseudo	`bgt s, t, label` Branch to label if signed s > signed t. Expands to a comparison and a conditional branch. `bgt $t0, $t1, greater` Expansion · 2 real instructions · no opcode of its own The expansion below follows the pinned MARS register-operand form. $at is register $1; reserve it for the assembler. The expansion ends in a real branch; its following instruction is the delay slot when delayed branching is enabled. MARS does not automatically append a nop for these ordinary branch pseudos. slt $at, t, s bne $at, $zero, label Symbolic operands d/s/t stand for registers. Click a real mnemonic above to see its encoding. bgt $t1,$t2,label is the source template form. ac3d34ea65c3.
bge # Pseudo	`bge s, t, label` Branch to label if signed s ≥ signed t. Expands to a comparison and a conditional branch. `bge $t0, $t1, greater_or_equal` Expansion · 2 real instructions · no opcode of its own The expansion below follows the pinned MARS register-operand form. $at is register $1; reserve it for the assembler. The expansion ends in a real branch; its following instruction is the delay slot when delayed branching is enabled. MARS does not automatically append a nop for these ordinary branch pseudos. slt $at, s, t beq $at, $zero, label Symbolic operands d/s/t stand for registers. Click a real mnemonic above to see its encoding. bge $t1,$t2,label is the source template form. ac3d34ea65c3.
bltu # Pseudo	`bltu s, t, label` Branch to label if unsigned s < unsigned t. Expands to an unsigned comparison and a conditional branch. `bltu $t0, $t1, unsigned_less` Expansion · 2 real instructions · no opcode of its own The expansion below follows the pinned MARS register-operand form. $at is register $1; reserve it for the assembler. The expansion ends in a real branch; its following instruction is the delay slot when delayed branching is enabled. MARS does not automatically append a nop for these ordinary branch pseudos. sltu $at, s, t bne $at, $zero, label Symbolic operands d/s/t stand for registers. Click a real mnemonic above to see its encoding. bltu $t1,$t2,label is the source template form. ac3d34ea65c3.
bleu # Pseudo	`bleu s, t, label` Branch to label if unsigned s ≤ unsigned t. Expands to an unsigned comparison and a conditional branch. `bleu $t0, $t1, unsigned_less_or_equal` Expansion · 2 real instructions · no opcode of its own The expansion below follows the pinned MARS register-operand form. $at is register $1; reserve it for the assembler. The expansion ends in a real branch; its following instruction is the delay slot when delayed branching is enabled. MARS does not automatically append a nop for these ordinary branch pseudos. sltu $at, t, s beq $at, $zero, label Symbolic operands d/s/t stand for registers. Click a real mnemonic above to see its encoding. bleu $t1,$t2,label is the source template form. ac3d34ea65c3.
bgtu # Pseudo	`bgtu s, t, label` Branch to label if unsigned s > unsigned t. Expands to an unsigned comparison and a conditional branch. `bgtu $t0, $t1, unsigned_greater` Expansion · 2 real instructions · no opcode of its own The expansion below follows the pinned MARS register-operand form. $at is register $1; reserve it for the assembler. The expansion ends in a real branch; its following instruction is the delay slot when delayed branching is enabled. MARS does not automatically append a nop for these ordinary branch pseudos. sltu $at, t, s bne $at, $zero, label Symbolic operands d/s/t stand for registers. Click a real mnemonic above to see its encoding. bgtu $t1,$t2,label is the source template form. ac3d34ea65c3.
bgeu # Pseudo	`bgeu s, t, label` Branch to label if unsigned s ≥ unsigned t. Expands to an unsigned comparison and a conditional branch. `bgeu $t0, $t1, unsigned_greater_or_equal` Expansion · 2 real instructions · no opcode of its own The expansion below follows the pinned MARS register-operand form. $at is register $1; reserve it for the assembler. The expansion ends in a real branch; its following instruction is the delay slot when delayed branching is enabled. MARS does not automatically append a nop for these ordinary branch pseudos. sltu $at, s, t beq $at, $zero, label Symbolic operands d/s/t stand for registers. Click a real mnemonic above to see its encoding. bgeu $t1,$t2,label is the source template form. ac3d34ea65c3.
b # Pseudo	`b label` Unconditional branch; commonly beq $zero, $zero, label. `b loop` Expansion · 1 real instructions · no opcode of its own Pinned MARS expansion for this operand form. The expansion ends in a real branch; its following instruction is the delay slot when delayed branching is enabled. MARS does not automatically append a nop for these ordinary branch pseudos. bgez $zero, label Symbolic operands d/s/t stand for registers. Click a real mnemonic above to see its encoding. b label is the source template form. ac3d34ea65c3.
seq # Pseudo	`seq d, s, t` Write 1 to d if s equals t; otherwise write 0. Equality compares the bit patterns. `seq $t0, $t1, $t2` Expansion · 3 real instructions · no opcode of its own The expansion below follows the pinned MARS register-operand form. $at is register $1; reserve it for the assembler. subu d, s, t ori $at, $zero, 1 sltu d, d, $at Symbolic operands d/s/t stand for registers. Click a real mnemonic above to see its encoding. seq $t1,$t2,$t3 is the source template form. ac3d34ea65c3.
sne # Pseudo	`sne d, s, t` Write 1 to d if s differs from t; otherwise write 0. Equality compares the bit patterns. `sne $t0, $t1, $t2` Expansion · 2 real instructions · no opcode of its own Pinned MARS expansion for this operand form. subu d, s, t sltu d, $zero, d Symbolic operands d/s/t stand for registers. Click a real mnemonic above to see its encoding. sne $t1,$t2,$t3 is the source template form. ac3d34ea65c3.
sle # Pseudo	`sle d, s, t` Write 1 to d if signed s ≤ signed t; otherwise write 0. `sle $t0, $t1, $t2` Expansion · 3 real instructions · no opcode of its own The expansion below follows the pinned MARS register-operand form. $at is register $1; reserve it for the assembler. slt d, t, s ori $at, $zero, 1 subu d, $at, d Symbolic operands d/s/t stand for registers. Click a real mnemonic above to see its encoding. sle $t1,$t2,$t3 is the source template form. ac3d34ea65c3.
sge # Pseudo	`sge d, s, t` Write 1 to d if signed s ≥ signed t; otherwise write 0. `sge $t0, $t1, $t2` Expansion · 3 real instructions · no opcode of its own The expansion below follows the pinned MARS register-operand form. $at is register $1; reserve it for the assembler. slt d, s, t ori $at, $zero, 1 subu d, $at, d Symbolic operands d/s/t stand for registers. Click a real mnemonic above to see its encoding. sge $t1,$t2,$t3 is the source template form. ac3d34ea65c3.
sgt # Pseudo	`sgt d, s, t` Write 1 to d if signed s > signed t; otherwise write 0. `sgt $t0, $t1, $t2` Expansion · 1 real instructions · no opcode of its own Pinned MARS expansion for this operand form. slt d, t, s Symbolic operands d/s/t stand for registers. Click a real mnemonic above to see its encoding. sgt $t1,$t2,$t3 is the source template form. ac3d34ea65c3.

Memory and addresses

Instruction	Syntax, meaning and example
lw # Real	`lw t, offset(s)` Load a 32-bit word from memory into t. Address = s + sign-extended 16-bit byte offset. The address must be a multiple of 4. `lw $t0, 12($sp) # t0 = word at sp + 12` I format · opcode 35 (0x23) · no funct opcode [6]`100011`35 (0x23)rs [5]`s`rt [5]`t`immediate [16]`offset` Fields run from bit 31 on the left to bit 0 on the right. Brackets show widths. Field values use decimal followed by hexadecimal, alongside the binary bits. Immediate fields show their unsigned raw bits; signed interpretation depends on the instruction. The offset is signed and measured in bytes. The rt field identifies the value register, including for stores. Example word: `2410151948 (0x8FA8000C)` 1000 1111 1010 1000 0000 0000 0000 1100 Encoding checked against pinned MARS ac3d34ea65c3.
sw # Real	`sw t, offset(s)` Store all 32 bits of t to memory. Address = s + sign-extended 16-bit byte offset. The address must be a multiple of 4; t is not modified. `sw $t0, 12($sp) # word at sp + 12 = t0` I format · opcode 43 (0x2B) · no funct opcode [6]`101011`43 (0x2B)rs [5]`s`rt [5]`t`immediate [16]`offset` Fields run from bit 31 on the left to bit 0 on the right. Brackets show widths. Field values use decimal followed by hexadecimal, alongside the binary bits. Immediate fields show their unsigned raw bits; signed interpretation depends on the instruction. The offset is signed and measured in bytes. The rt field identifies the value register, including for stores. Example word: `2947022860 (0xAFA8000C)` 1010 1111 1010 1000 0000 0000 0000 1100 Encoding checked against pinned MARS ac3d34ea65c3.
lb # Real	`lb t, offset(s)` Load one 8-bit byte from memory into t and sign-extend it to 32 bits. Address = s + sign-extended 16-bit byte offset; no alignment restriction. `lb $t0, 0($a0) # 0xff becomes 0xffffffff` I format · opcode 32 (0x20) · no funct opcode [6]`100000`32 (0x20)rs [5]`s`rt [5]`t`immediate [16]`offset` Fields run from bit 31 on the left to bit 0 on the right. Brackets show widths. Field values use decimal followed by hexadecimal, alongside the binary bits. Immediate fields show their unsigned raw bits; signed interpretation depends on the instruction. The offset is signed and measured in bytes. The rt field identifies the value register, including for stores. Example word: `2156396544 (0x80880000)` 1000 0000 1000 1000 0000 0000 0000 0000 Encoding checked against pinned MARS ac3d34ea65c3.
lbu # Real	`lbu t, offset(s)` Load one 8-bit byte from memory into t and zero-extend it to 32 bits. Address = s + sign-extended 16-bit byte offset; no alignment restriction. `lbu $t0, 0($a0) # 0xff becomes 0x000000ff` I format · opcode 36 (0x24) · no funct opcode [6]`100100`36 (0x24)rs [5]`s`rt [5]`t`immediate [16]`offset` Fields run from bit 31 on the left to bit 0 on the right. Brackets show widths. Field values use decimal followed by hexadecimal, alongside the binary bits. Immediate fields show their unsigned raw bits; signed interpretation depends on the instruction. The offset is signed and measured in bytes. The rt field identifies the value register, including for stores. Example word: `2424832000 (0x90880000)` 1001 0000 1000 1000 0000 0000 0000 0000 Encoding checked against pinned MARS ac3d34ea65c3.
lh # Real	`lh t, offset(s)` Load one 16-bit halfword from memory into t and sign-extend it to 32 bits. Address = s + sign-extended 16-bit byte offset; requires 2-byte alignment. `lh $t0, 2($a0) # 0xffff becomes 0xffffffff` I format · opcode 33 (0x21) · no funct opcode [6]`100001`33 (0x21)rs [5]`s`rt [5]`t`immediate [16]`offset` Fields run from bit 31 on the left to bit 0 on the right. Brackets show widths. Field values use decimal followed by hexadecimal, alongside the binary bits. Immediate fields show their unsigned raw bits; signed interpretation depends on the instruction. The offset is signed and measured in bytes. The rt field identifies the value register, including for stores. Example word: `2223505410 (0x84880002)` 1000 0100 1000 1000 0000 0000 0000 0010 Encoding checked against pinned MARS ac3d34ea65c3.
lhu # Real	`lhu t, offset(s)` Load one 16-bit halfword from memory into t and zero-extend it to 32 bits. Address = s + sign-extended 16-bit byte offset; requires 2-byte alignment. `lhu $t0, 2($a0) # 0xffff becomes 0x0000ffff` I format · opcode 37 (0x25) · no funct opcode [6]`100101`37 (0x25)rs [5]`s`rt [5]`t`immediate [16]`offset` Fields run from bit 31 on the left to bit 0 on the right. Brackets show widths. Field values use decimal followed by hexadecimal, alongside the binary bits. Immediate fields show their unsigned raw bits; signed interpretation depends on the instruction. The offset is signed and measured in bytes. The rt field identifies the value register, including for stores. Example word: `2491940866 (0x94880002)` 1001 0100 1000 1000 0000 0000 0000 0010 Encoding checked against pinned MARS ac3d34ea65c3.
sb # Real	`sb t, offset(s)` Store the low 8 bits of t to one byte of memory. Address = s + sign-extended 16-bit byte offset; no alignment restriction. The register is unchanged. `sb $t0, 0($a0) # store low byte of t0` I format · opcode 40 (0x28) · no funct opcode [6]`101000`40 (0x28)rs [5]`s`rt [5]`t`immediate [16]`offset` Fields run from bit 31 on the left to bit 0 on the right. Brackets show widths. Field values use decimal followed by hexadecimal, alongside the binary bits. Immediate fields show their unsigned raw bits; signed interpretation depends on the instruction. The offset is signed and measured in bytes. The rt field identifies the value register, including for stores. Example word: `2693267456 (0xA0880000)` 1010 0000 1000 1000 0000 0000 0000 0000 Encoding checked against pinned MARS ac3d34ea65c3.
sh # Real	`sh t, offset(s)` Store the low 16 bits of t to a halfword of memory. Address = s + sign-extended 16-bit byte offset; requires 2-byte alignment. The register is unchanged. `sh $t0, 2($a0) # store low halfword of t0` I format · opcode 41 (0x29) · no funct opcode [6]`101001`41 (0x29)rs [5]`s`rt [5]`t`immediate [16]`offset` Fields run from bit 31 on the left to bit 0 on the right. Brackets show widths. Field values use decimal followed by hexadecimal, alongside the binary bits. Immediate fields show their unsigned raw bits; signed interpretation depends on the instruction. The offset is signed and measured in bytes. The rt field identifies the value register, including for stores. Example word: `2760376322 (0xA4880002)` 1010 0100 1000 1000 0000 0000 0000 0010 Encoding checked against pinned MARS ac3d34ea65c3.
la # Pseudo	`la d, label` Load the address of a label, without reading the contents at that address. `la $t0, array` Expansion · 1–2 real instructions · no opcode of its own Default: 2 real instructions and $at is clobbered. The compact alternative applies only to a suitable MARS compact memory configuration and a signed 16-bit address. Other assemblers and relocation models may expand la differently. # Default MARS label form: lui $at, upper16(address(label)) ori d, $at, lower16(address(label)) # MARS compact-address alternative: addi d, $zero, address(label) Symbolic operands d/s/t stand for registers. Click a real mnemonic above to see its encoding. la $t1,label is the source template form. ac3d34ea65c3.
li # Pseudo	`li d, value` Load a constant; may expand to one or several real instructions. `li $t0, 0x12345678` Expansion · 1–2 real instructions · no opcode of its own 1 or 2 real instructions, depending on the accepted immediate form. upper16 is bits 31:16; lower16 is bits 15:0, used by ori without sign extension. The full-width pinned MARS template clobbers $at. # Signed 16-bit constant: addiu d, $zero, imm16 # Unsigned 16-bit constant: ori d, $zero, imm16 # General 32-bit constant: lui $at, upper16(value) ori d, $at, lower16(value) Symbolic operands d/s/t stand for registers. Click a real mnemonic above to see its encoding. li is the source template form. ac3d34ea65c3.
move # Pseudo	`move d, s` Copy a register; commonly implemented as addu d, s, $zero. `move $s0, $a0` Expansion · 1 real instructions · no opcode of its own Pinned MARS expansion for this operand form. addu d, $zero, s Symbolic operands d/s/t stand for registers. Click a real mnemonic above to see its encoding. move $t1,$t2 is the source template form. ac3d34ea65c3.

Jumps and calls

Instruction	Syntax, meaning and example
j # Real	`j label` Jump using a pseudo-direct target encoding; cannot encode every 32-bit address. `j done` J format · opcode 2 (0x02) · no funct opcode [6]`000010`2 (0x02)index [26]`jumpIndex` Fields run from bit 31 on the left to bit 0 on the right. Brackets show widths. Field values use decimal followed by hexadecimal, alongside the binary bits. Immediate fields show their unsigned raw bits; signed interpretation depends on the instruction. Target = {(PC+4)[31:28], index[25:0], 00}. The index is a word index, not a byte address. Example word: `135266312 (0x08100008)` 0000 1000 0001 0000 0000 0000 0000 1000 For this encoded example, assume PC = 0x00400000 and label = 0x00400020. The label in the example is illustrative. Encoding checked against pinned MARS ac3d34ea65c3.
jal # Real	`jal label` Call a function and write the return address to $ra. The saved address depends on delay-slot execution mode. `jal sum_array` J format · opcode 3 (0x03) · no funct opcode [6]`000011`3 (0x03)index [26]`jumpIndex` Fields run from bit 31 on the left to bit 0 on the right. Brackets show widths. Field values use decimal followed by hexadecimal, alongside the binary bits. Immediate fields show their unsigned raw bits; signed interpretation depends on the instruction. Target = {(PC+4)[31:28], index[25:0], 00}. The index is a word index, not a byte address. Example word: `202375176 (0x0C100008)` 0000 1100 0001 0000 0000 0000 0000 1000 For this encoded example, assume PC = 0x00400000 and label = 0x00400020. The label in the example is illustrative. Encoding checked against pinned MARS ac3d34ea65c3.
jr # Real	`jr s` Jump to the address in a register; jr $ra is the usual return sequence. `jr $ra` R format · opcode 0 (0x00) · funct 8 (0x08) opcode [6]`000000`0 (0x00)rs [5]`s`rt [5]`00000`0 (0x00)rd [5]`00000`0 (0x00)shamt [5]`00000`0 (0x00)funct [6]`001000`8 (0x08) Fields run from bit 31 on the left to bit 0 on the right. Brackets show widths. Field values use decimal followed by hexadecimal, alongside the binary bits. Immediate fields show their unsigned raw bits; signed interpretation depends on the instruction. Register fields contain 5-bit register numbers. Unused fields shown as zero must be zero in this form. Example word: `65011720 (0x03E00008)` 0000 0011 1110 0000 0000 0000 0000 1000 Encoding checked against pinned MARS ac3d34ea65c3.
jalr # Real	`jalr d, s` Jump to the address in s and save the return address in d; commonly d = $ra. `jalr $ra, $t9` R format · opcode 0 (0x00) · funct 9 (0x09) opcode [6]`000000`0 (0x00)rs [5]`s`rt [5]`00000`0 (0x00)rd [5]`d`shamt [5]`00000`0 (0x00)funct [6]`001001`9 (0x09) Fields run from bit 31 on the left to bit 0 on the right. Brackets show widths. Field values use decimal followed by hexadecimal, alongside the binary bits. Immediate fields show their unsigned raw bits; signed interpretation depends on the instruction. Register fields contain 5-bit register numbers. Unused fields shown as zero must be zero in this form. Example word: `52492297 (0x0320F809)` 0000 0011 0010 0000 1111 1000 0000 1001 Encoding checked against pinned MARS ac3d34ea65c3.
nop # Alias	`nop` Do nothing; identical encoding to sll $zero, $zero, 0. MARS lists nop as a basic instruction. `nop` R format · opcode 0 (0x00) · funct 0 (0x00) opcode [6]`000000`0 (0x00)rs [5]`00000`0 (0x00)rt [5]`00000`0 (0x00)rd [5]`00000`0 (0x00)shamt [5]`00000`0 (0x00)funct [6]`000000`0 (0x00) Fields run from bit 31 on the left to bit 0 on the right. Brackets show widths. Field values use decimal followed by hexadecimal, alongside the binary bits. Immediate fields show their unsigned raw bits; signed interpretation depends on the instruction. Register fields contain 5-bit register numbers. Unused fields shown as zero must be zero in this form. Example word: `0 (0x00000000)` 0000 0000 0000 0000 0000 0000 0000 0000 Encoding checked against pinned MARS ac3d34ea65c3.
syscall # Real	`syscall` Enter a system-service handler. MARS selects a simulated service using $v0; service numbers are not defined by the MIPS ISA. `syscall` SPECIAL / code format · opcode 0 (0x00) · funct 12 (0x0C) opcode [6]`000000`0 (0x00)code [20]`00000000000000000000`0 (0x00)funct [6]`001100`12 (0x0C) Fields run from bit 31 on the left to bit 0 on the right. Brackets show widths. Field values use decimal followed by hexadecimal, alongside the binary bits. Immediate fields show their unsigned raw bits; signed interpretation depends on the instruction. This no-operand form uses code = 0. MIPS also has encoded code fields; MARS services use $v0, not this field. Example word: `12 (0x0000000C)` 0000 0000 0000 0000 0000 0000 0000 1100 Encoding checked against pinned MARS ac3d34ea65c3.
break # Real	`break` Raise a breakpoint exception; not a general substitute for exiting a program. `break` SPECIAL / code format · opcode 0 (0x00) · funct 13 (0x0D) opcode [6]`000000`0 (0x00)code [20]`00000000000000000000`0 (0x00)funct [6]`001101`13 (0x0D) Fields run from bit 31 on the left to bit 0 on the right. Brackets show widths. Field values use decimal followed by hexadecimal, alongside the binary bits. Immediate fields show their unsigned raw bits; signed interpretation depends on the instruction. This no-operand form uses code = 0. MIPS also has encoded code fields; MARS services use $v0, not this field. Example word: `13 (0x0000000D)` 0000 0000 0000 0000 0000 0000 0000 1101 Encoding checked against pinned MARS ac3d34ea65c3.

Common floating-point instructions

Instruction	Syntax, meaning and example
lwc1 # Real	`lwc1 ft, offset(s)` Load a 32-bit word from memory into floating-point register ft. Copy the raw bits without numerical conversion; requires 4-byte alignment. `lwc1 $f0, 0($a0)` I format · opcode 49 (0x31) · no funct opcode [6]`110001`49 (0x31)rs [5]`s`rt [5]`ft`immediate [16]`offset` Fields run from bit 31 on the left to bit 0 on the right. Brackets show widths. Field values use decimal followed by hexadecimal, alongside the binary bits. Immediate fields show their unsigned raw bits; signed interpretation depends on the instruction. The offset is signed and measured in bytes. The rt field identifies a floating-point register. Example word: `3296722944 (0xC4800000)` 1100 0100 1000 0000 0000 0000 0000 0000 Encoding checked against pinned MARS ac3d34ea65c3.
swc1 # Real	`swc1 ft, offset(s)` Store the 32-bit bit pattern in floating-point register ft to memory without numerical conversion. Requires 4-byte alignment; ft is unchanged. `swc1 $f0, 0($a0)` I format · opcode 57 (0x39) · no funct opcode [6]`111001`57 (0x39)rs [5]`s`rt [5]`ft`immediate [16]`offset` Fields run from bit 31 on the left to bit 0 on the right. Brackets show widths. Field values use decimal followed by hexadecimal, alongside the binary bits. Immediate fields show their unsigned raw bits; signed interpretation depends on the instruction. The offset is signed and measured in bytes. The rt field identifies a floating-point register. Example word: `3833593856 (0xE4800000)` 1110 0100 1000 0000 0000 0000 0000 0000 Encoding checked against pinned MARS ac3d34ea65c3.
ldc1 # Real	`ldc1 ft, offset(s)` Load 64 bits from memory into a floating-point register pair. In MARS, ft must be even-numbered and the memory address must be 8-byte aligned. `ldc1 $f2, 0($a0)` I format · opcode 53 (0x35) · no funct opcode [6]`110101`53 (0x35)rs [5]`s`rt [5]`ft`immediate [16]`offset` Fields run from bit 31 on the left to bit 0 on the right. Brackets show widths. Field values use decimal followed by hexadecimal, alongside the binary bits. Immediate fields show their unsigned raw bits; signed interpretation depends on the instruction. The offset is signed and measured in bytes. The rt field identifies a floating-point register. Example word: `3565289472 (0xD4820000)` 1101 0100 1000 0010 0000 0000 0000 0000 Encoding checked against pinned MARS ac3d34ea65c3.
sdc1 # Real	`sdc1 ft, offset(s)` Store the 64-bit bit pattern in a floating-point register pair to memory. In MARS, ft must be even-numbered; requires 8-byte alignment. The register pair is unchanged. `sdc1 $f2, 0($a0)` I format · opcode 61 (0x3D) · no funct opcode [6]`111101`61 (0x3D)rs [5]`s`rt [5]`ft`immediate [16]`offset` Fields run from bit 31 on the left to bit 0 on the right. Brackets show widths. Field values use decimal followed by hexadecimal, alongside the binary bits. Immediate fields show their unsigned raw bits; signed interpretation depends on the instruction. The offset is signed and measured in bytes. The rt field identifies a floating-point register. Example word: `4102160384 (0xF4820000)` 1111 0100 1000 0010 0000 0000 0000 0000 Encoding checked against pinned MARS ac3d34ea65c3.
mtc1 # Real	`mtc1 t, fs` Copy the 32-bit bit pattern in general-purpose register t to floating-point register fs. This is not an integer-to-float numerical conversion. `mtc1 $t0, $f0` COP1 / transfer format · opcode 17 (0x11) · no funct opcode [6]`010001`17 (0x11)rs [5]`00100`4 (0x04)rt [5]`t`fs [5]`fs`reserved [11]`00000000000`0 (0x00) Fields run from bit 31 on the left to bit 0 on the right. Brackets show widths. Field values use decimal followed by hexadecimal, alongside the binary bits. Immediate fields show their unsigned raw bits; signed interpretation depends on the instruction. rs selects the transfer direction. There is no floating-point arithmetic funct field in this format. Example word: `1149763584 (0x44880000)` 0100 0100 1000 1000 0000 0000 0000 0000 Encoding checked against pinned MARS ac3d34ea65c3.
mfc1 # Real	`mfc1 t, fs` Copy the 32-bit bit pattern in floating-point register fs to general-purpose register t. This is not a float-to-integer numerical conversion. `mfc1 $t0, $f0` COP1 / transfer format · opcode 17 (0x11) · no funct opcode [6]`010001`17 (0x11)rs [5]`00000`0 (0x00)rt [5]`t`fs [5]`fs`reserved [11]`00000000000`0 (0x00) Fields run from bit 31 on the left to bit 0 on the right. Brackets show widths. Field values use decimal followed by hexadecimal, alongside the binary bits. Immediate fields show their unsigned raw bits; signed interpretation depends on the instruction. rs selects the transfer direction. There is no floating-point arithmetic funct field in this format. Example word: `1141374976 (0x44080000)` 0100 0100 0000 1000 0000 0000 0000 0000 Encoding checked against pinned MARS ac3d34ea65c3.
add.s # Real	`add.s fd, fs, ft` Add fs and ft using single-precision floating-point arithmetic and write the result to fd. `add.s $f4, $f0, $f2` COP1 / arithmetic format · opcode 17 (0x11) · funct 0 (0x00) · fmt 16 (0x10) opcode [6]`010001`17 (0x11)fmt [5]`10000`16 (0x10)ft [5]`ft`fs [5]`fs`fd [5]`fd`funct [6]`000000`0 (0x00) Fields run from bit 31 on the left to bit 0 on the right. Brackets show widths. Field values use decimal followed by hexadecimal, alongside the binary bits. Immediate fields show their unsigned raw bits; signed interpretation depends on the instruction. fmt describes the source representation: S = 16 (0x10), D = 17 (0x11), W = 20 (0x14). Example word: `1174536448 (0x46020100)` 0100 0110 0000 0010 0000 0001 0000 0000 Encoding checked against pinned MARS ac3d34ea65c3.
sub.s # Real	`sub.s fd, fs, ft` Subtract ft from fs using single-precision floating-point arithmetic and write the result to fd. `sub.s $f4, $f0, $f2` COP1 / arithmetic format · opcode 17 (0x11) · funct 1 (0x01) · fmt 16 (0x10) opcode [6]`010001`17 (0x11)fmt [5]`10000`16 (0x10)ft [5]`ft`fs [5]`fs`fd [5]`fd`funct [6]`000001`1 (0x01) Fields run from bit 31 on the left to bit 0 on the right. Brackets show widths. Field values use decimal followed by hexadecimal, alongside the binary bits. Immediate fields show their unsigned raw bits; signed interpretation depends on the instruction. fmt describes the source representation: S = 16 (0x10), D = 17 (0x11), W = 20 (0x14). Example word: `1174536449 (0x46020101)` 0100 0110 0000 0010 0000 0001 0000 0001 Encoding checked against pinned MARS ac3d34ea65c3.
mul.s # Real	`mul.s fd, fs, ft` Multiply fs by ft using single-precision floating-point arithmetic and write the result to fd. `mul.s $f4, $f0, $f2` COP1 / arithmetic format · opcode 17 (0x11) · funct 2 (0x02) · fmt 16 (0x10) opcode [6]`010001`17 (0x11)fmt [5]`10000`16 (0x10)ft [5]`ft`fs [5]`fs`fd [5]`fd`funct [6]`000010`2 (0x02) Fields run from bit 31 on the left to bit 0 on the right. Brackets show widths. Field values use decimal followed by hexadecimal, alongside the binary bits. Immediate fields show their unsigned raw bits; signed interpretation depends on the instruction. fmt describes the source representation: S = 16 (0x10), D = 17 (0x11), W = 20 (0x14). Example word: `1174536450 (0x46020102)` 0100 0110 0000 0010 0000 0001 0000 0010 Encoding checked against pinned MARS ac3d34ea65c3.
div.s # Real	`div.s fd, fs, ft` Divide fs by ft using single-precision floating-point arithmetic and write the result to fd. `div.s $f4, $f0, $f2` COP1 / arithmetic format · opcode 17 (0x11) · funct 3 (0x03) · fmt 16 (0x10) opcode [6]`010001`17 (0x11)fmt [5]`10000`16 (0x10)ft [5]`ft`fs [5]`fs`fd [5]`fd`funct [6]`000011`3 (0x03) Fields run from bit 31 on the left to bit 0 on the right. Brackets show widths. Field values use decimal followed by hexadecimal, alongside the binary bits. Immediate fields show their unsigned raw bits; signed interpretation depends on the instruction. fmt describes the source representation: S = 16 (0x10), D = 17 (0x11), W = 20 (0x14). Example word: `1174536451 (0x46020103)` 0100 0110 0000 0010 0000 0001 0000 0011 Encoding checked against pinned MARS ac3d34ea65c3.
add.d # Real	`add.d fd, fs, ft` Add fs and ft using double-precision floating-point arithmetic and write the result to fd. In MARS, all operands are register pairs starting at even-numbered registers. `add.d $f8, $f4, $f6` COP1 / arithmetic format · opcode 17 (0x11) · funct 0 (0x00) · fmt 17 (0x11) opcode [6]`010001`17 (0x11)fmt [5]`10001`17 (0x11)ft [5]`ft`fs [5]`fs`fd [5]`fd`funct [6]`000000`0 (0x00) Fields run from bit 31 on the left to bit 0 on the right. Brackets show widths. Field values use decimal followed by hexadecimal, alongside the binary bits. Immediate fields show their unsigned raw bits; signed interpretation depends on the instruction. fmt describes the source representation: S = 16 (0x10), D = 17 (0x11), W = 20 (0x14). Example word: `1176904192 (0x46262200)` 0100 0110 0010 0110 0010 0010 0000 0000 Encoding checked against pinned MARS ac3d34ea65c3.
sub.d # Real	`sub.d fd, fs, ft` Subtract ft from fs using double-precision floating-point arithmetic and write the result to fd. In MARS, all operands are register pairs starting at even-numbered registers. `sub.d $f8, $f4, $f6` COP1 / arithmetic format · opcode 17 (0x11) · funct 1 (0x01) · fmt 17 (0x11) opcode [6]`010001`17 (0x11)fmt [5]`10001`17 (0x11)ft [5]`ft`fs [5]`fs`fd [5]`fd`funct [6]`000001`1 (0x01) Fields run from bit 31 on the left to bit 0 on the right. Brackets show widths. Field values use decimal followed by hexadecimal, alongside the binary bits. Immediate fields show their unsigned raw bits; signed interpretation depends on the instruction. fmt describes the source representation: S = 16 (0x10), D = 17 (0x11), W = 20 (0x14). Example word: `1176904193 (0x46262201)` 0100 0110 0010 0110 0010 0010 0000 0001 Encoding checked against pinned MARS ac3d34ea65c3.
mul.d # Real	`mul.d fd, fs, ft` Multiply fs by ft using double-precision floating-point arithmetic and write the result to fd. In MARS, all operands are register pairs starting at even-numbered registers. `mul.d $f8, $f4, $f6` COP1 / arithmetic format · opcode 17 (0x11) · funct 2 (0x02) · fmt 17 (0x11) opcode [6]`010001`17 (0x11)fmt [5]`10001`17 (0x11)ft [5]`ft`fs [5]`fs`fd [5]`fd`funct [6]`000010`2 (0x02) Fields run from bit 31 on the left to bit 0 on the right. Brackets show widths. Field values use decimal followed by hexadecimal, alongside the binary bits. Immediate fields show their unsigned raw bits; signed interpretation depends on the instruction. fmt describes the source representation: S = 16 (0x10), D = 17 (0x11), W = 20 (0x14). Example word: `1176904194 (0x46262202)` 0100 0110 0010 0110 0010 0010 0000 0010 Encoding checked against pinned MARS ac3d34ea65c3.
div.d # Real	`div.d fd, fs, ft` Divide fs by ft using double-precision floating-point arithmetic and write the result to fd. In MARS, all operands are register pairs starting at even-numbered registers. `div.d $f8, $f4, $f6` COP1 / arithmetic format · opcode 17 (0x11) · funct 3 (0x03) · fmt 17 (0x11) opcode [6]`010001`17 (0x11)fmt [5]`10001`17 (0x11)ft [5]`ft`fs [5]`fs`fd [5]`fd`funct [6]`000011`3 (0x03) Fields run from bit 31 on the left to bit 0 on the right. Brackets show widths. Field values use decimal followed by hexadecimal, alongside the binary bits. Immediate fields show their unsigned raw bits; signed interpretation depends on the instruction. fmt describes the source representation: S = 16 (0x10), D = 17 (0x11), W = 20 (0x14). Example word: `1176904195 (0x46262203)` 0100 0110 0010 0110 0010 0010 0000 0011 Encoding checked against pinned MARS ac3d34ea65c3.
mov.s # Real	`mov.s fd, fs` Copy a single-precision floating-point value from fs to fd. `mov.s $f12, $f0` COP1 / arithmetic format · opcode 17 (0x11) · funct 6 (0x06) · fmt 16 (0x10) opcode [6]`010001`17 (0x11)fmt [5]`10000`16 (0x10)ft [5]`00000`0 (0x00)fs [5]`fs`fd [5]`fd`funct [6]`000110`6 (0x06) Fields run from bit 31 on the left to bit 0 on the right. Brackets show widths. Field values use decimal followed by hexadecimal, alongside the binary bits. Immediate fields show their unsigned raw bits; signed interpretation depends on the instruction. fmt describes the source representation: S = 16 (0x10), D = 17 (0x11), W = 20 (0x14). Example word: `1174405894 (0x46000306)` 0100 0110 0000 0000 0000 0011 0000 0110 Encoding checked against pinned MARS ac3d34ea65c3.
mov.d # Real	`mov.d fd, fs` Copy a double-precision floating-point value from fs to fd. In MARS, source and destination are register pairs starting at even-numbered registers. `mov.d $f12, $f0` COP1 / arithmetic format · opcode 17 (0x11) · funct 6 (0x06) · fmt 17 (0x11) opcode [6]`010001`17 (0x11)fmt [5]`10001`17 (0x11)ft [5]`00000`0 (0x00)fs [5]`fs`fd [5]`fd`funct [6]`000110`6 (0x06) Fields run from bit 31 on the left to bit 0 on the right. Brackets show widths. Field values use decimal followed by hexadecimal, alongside the binary bits. Immediate fields show their unsigned raw bits; signed interpretation depends on the instruction. fmt describes the source representation: S = 16 (0x10), D = 17 (0x11), W = 20 (0x14). Example word: `1176503046 (0x46200306)` 0100 0110 0010 0000 0000 0011 0000 0110 Encoding checked against pinned MARS ac3d34ea65c3.
cvt.s.w # Real	`cvt.s.w fd, fs` Interpret the 32 bits in fs as a signed integer and convert that integer to a single-precision value in fd. The destination is a floating-point register. `cvt.s.w $f2, $f0` COP1 / arithmetic format · opcode 17 (0x11) · funct 32 (0x20) · fmt 20 (0x14) opcode [6]`010001`17 (0x11)fmt [5]`10100`20 (0x14)ft [5]`00000`0 (0x00)fs [5]`fs`fd [5]`fd`funct [6]`100000`32 (0x20) Fields run from bit 31 on the left to bit 0 on the right. Brackets show widths. Field values use decimal followed by hexadecimal, alongside the binary bits. Immediate fields show their unsigned raw bits; signed interpretation depends on the instruction. fmt describes the source representation: S = 16 (0x10), D = 17 (0x11), W = 20 (0x14). Example word: `1182793888 (0x468000A0)` 0100 0110 1000 0000 0000 0000 1010 0000 Encoding checked against pinned MARS ac3d34ea65c3.
cvt.d.w # Real	`cvt.d.w fd, fs` Interpret the 32 bits in fs as a signed integer and convert that integer to double precision. In MARS, fd names a register pair starting at an even-numbered register. `cvt.d.w $f2, $f0` COP1 / arithmetic format · opcode 17 (0x11) · funct 33 (0x21) · fmt 20 (0x14) opcode [6]`010001`17 (0x11)fmt [5]`10100`20 (0x14)ft [5]`00000`0 (0x00)fs [5]`fs`fd [5]`fd`funct [6]`100001`33 (0x21) Fields run from bit 31 on the left to bit 0 on the right. Brackets show widths. Field values use decimal followed by hexadecimal, alongside the binary bits. Immediate fields show their unsigned raw bits; signed interpretation depends on the instruction. fmt describes the source representation: S = 16 (0x10), D = 17 (0x11), W = 20 (0x14). Example word: `1182793889 (0x468000A1)` 0100 0110 1000 0000 0000 0000 1010 0001 Encoding checked against pinned MARS ac3d34ea65c3.
cvt.w.s # Real	`cvt.w.s fd, fs` Convert the single-precision value in fs to a signed 32-bit integer using the rounding mode. Store the integer bit pattern in fd; use mfc1 to retrieve it. `cvt.w.s $f2, $f0` COP1 / arithmetic format · opcode 17 (0x11) · funct 36 (0x24) · fmt 16 (0x10) opcode [6]`010001`17 (0x11)fmt [5]`10000`16 (0x10)ft [5]`00000`0 (0x00)fs [5]`fs`fd [5]`fd`funct [6]`100100`36 (0x24) Fields run from bit 31 on the left to bit 0 on the right. Brackets show widths. Field values use decimal followed by hexadecimal, alongside the binary bits. Immediate fields show their unsigned raw bits; signed interpretation depends on the instruction. fmt describes the source representation: S = 16 (0x10), D = 17 (0x11), W = 20 (0x14). Example word: `1174405284 (0x460000A4)` 0100 0110 0000 0000 0000 0000 1010 0100 Encoding checked against pinned MARS ac3d34ea65c3.
cvt.w.d # Real	`cvt.w.d fd, fs` Convert the double-precision value in fs to a signed 32-bit integer using the rounding mode. Store the integer bit pattern in fd; use mfc1 to retrieve it. In MARS, fs must be even-numbered. `cvt.w.d $f2, $f0` COP1 / arithmetic format · opcode 17 (0x11) · funct 36 (0x24) · fmt 17 (0x11) opcode [6]`010001`17 (0x11)fmt [5]`10001`17 (0x11)ft [5]`00000`0 (0x00)fs [5]`fs`fd [5]`fd`funct [6]`100100`36 (0x24) Fields run from bit 31 on the left to bit 0 on the right. Brackets show widths. Field values use decimal followed by hexadecimal, alongside the binary bits. Immediate fields show their unsigned raw bits; signed interpretation depends on the instruction. fmt describes the source representation: S = 16 (0x10), D = 17 (0x11), W = 20 (0x14). Example word: `1176502436 (0x462000A4)` 0100 0110 0010 0000 0000 0000 1010 0100 Encoding checked against pinned MARS ac3d34ea65c3.
trunc.w.s # Real	`trunc.w.s fd, fs` Convert the single-precision value in fs to a signed 32-bit integer by truncating toward zero. Store the integer bit pattern in fd; use mfc1 to retrieve it. `trunc.w.s $f2, $f0` COP1 / arithmetic format · opcode 17 (0x11) · funct 13 (0x0D) · fmt 16 (0x10) opcode [6]`010001`17 (0x11)fmt [5]`10000`16 (0x10)ft [5]`00000`0 (0x00)fs [5]`fs`fd [5]`fd`funct [6]`001101`13 (0x0D) Fields run from bit 31 on the left to bit 0 on the right. Brackets show widths. Field values use decimal followed by hexadecimal, alongside the binary bits. Immediate fields show their unsigned raw bits; signed interpretation depends on the instruction. fmt describes the source representation: S = 16 (0x10), D = 17 (0x11), W = 20 (0x14). Example word: `1174405261 (0x4600008D)` 0100 0110 0000 0000 0000 0000 1000 1101 Encoding checked against pinned MARS ac3d34ea65c3.
trunc.w.d # Real	`trunc.w.d fd, fs` Convert the double-precision value in fs to a signed 32-bit integer by truncating toward zero. Store the integer bit pattern in fd; use mfc1 to retrieve it. In MARS, fs must be even-numbered. `trunc.w.d $f2, $f0` COP1 / arithmetic format · opcode 17 (0x11) · funct 13 (0x0D) · fmt 17 (0x11) opcode [6]`010001`17 (0x11)fmt [5]`10001`17 (0x11)ft [5]`00000`0 (0x00)fs [5]`fs`fd [5]`fd`funct [6]`001101`13 (0x0D) Fields run from bit 31 on the left to bit 0 on the right. Brackets show widths. Field values use decimal followed by hexadecimal, alongside the binary bits. Immediate fields show their unsigned raw bits; signed interpretation depends on the instruction. fmt describes the source representation: S = 16 (0x10), D = 17 (0x11), W = 20 (0x14). Example word: `1176502413 (0x4620008D)` 0100 0110 0010 0000 0000 0000 1000 1101 Encoding checked against pinned MARS ac3d34ea65c3.
c.eq.s # Real	`c.eq.s fs, ft` Compare single-precision fs and ft. Set floating-point condition flag 0 if fs is equal to ft; clear it otherwise. `c.eq.s $f0, $f2` COP1 / compare format · opcode 17 (0x11) · funct 50 (0x32) · fmt 16 (0x10) opcode [6]`010001`17 (0x11)fmt [5]`10000`16 (0x10)ft [5]`ft`fs [5]`fs`cc [3]`000`0 (0x00)reserved [2]`00`0 (0x00)funct [6]`110010`50 (0x32) Fields run from bit 31 on the left to bit 0 on the right. Brackets show widths. Field values use decimal followed by hexadecimal, alongside the binary bits. Immediate fields show their unsigned raw bits; signed interpretation depends on the instruction. fmt describes the source representation: S = 16 (0x10), D = 17 (0x11), W = 20 (0x14). This two-operand form uses condition code cc = 0. Example word: `1174536242 (0x46020032)` 0100 0110 0000 0010 0000 0000 0011 0010 Encoding checked against pinned MARS ac3d34ea65c3.
c.lt.s # Real	`c.lt.s fs, ft` Compare single-precision fs and ft. Set floating-point condition flag 0 if fs is less than ft; clear it otherwise. `c.lt.s $f0, $f2` COP1 / compare format · opcode 17 (0x11) · funct 60 (0x3C) · fmt 16 (0x10) opcode [6]`010001`17 (0x11)fmt [5]`10000`16 (0x10)ft [5]`ft`fs [5]`fs`cc [3]`000`0 (0x00)reserved [2]`00`0 (0x00)funct [6]`111100`60 (0x3C) Fields run from bit 31 on the left to bit 0 on the right. Brackets show widths. Field values use decimal followed by hexadecimal, alongside the binary bits. Immediate fields show their unsigned raw bits; signed interpretation depends on the instruction. fmt describes the source representation: S = 16 (0x10), D = 17 (0x11), W = 20 (0x14). This two-operand form uses condition code cc = 0. Example word: `1174536252 (0x4602003C)` 0100 0110 0000 0010 0000 0000 0011 1100 Encoding checked against pinned MARS ac3d34ea65c3.
c.le.s # Real	`c.le.s fs, ft` Compare single-precision fs and ft. Set floating-point condition flag 0 if fs is less than or equal to ft; clear it otherwise. `c.le.s $f0, $f2` COP1 / compare format · opcode 17 (0x11) · funct 62 (0x3E) · fmt 16 (0x10) opcode [6]`010001`17 (0x11)fmt [5]`10000`16 (0x10)ft [5]`ft`fs [5]`fs`cc [3]`000`0 (0x00)reserved [2]`00`0 (0x00)funct [6]`111110`62 (0x3E) Fields run from bit 31 on the left to bit 0 on the right. Brackets show widths. Field values use decimal followed by hexadecimal, alongside the binary bits. Immediate fields show their unsigned raw bits; signed interpretation depends on the instruction. fmt describes the source representation: S = 16 (0x10), D = 17 (0x11), W = 20 (0x14). This two-operand form uses condition code cc = 0. Example word: `1174536254 (0x4602003E)` 0100 0110 0000 0010 0000 0000 0011 1110 Encoding checked against pinned MARS ac3d34ea65c3.
bc1t # Real	`bc1t label` Branch to label if floating-point condition flag 0 is true. This form uses the default condition code. `bc1t condition_true` COP1 / branch format · opcode 17 (0x11) · no funct opcode [6]`010001`17 (0x11)rs [5]`01000`8 (0x08)cc [3]`000`0 (0x00)nd [1]`0`0 (0x00)tf [1]`1`1 (0x01)offset [16]`branchOffset` Fields run from bit 31 on the left to bit 0 on the right. Brackets show widths. Field values use decimal followed by hexadecimal, alongside the binary bits. Immediate fields show their unsigned raw bits; signed interpretation depends on the instruction. cc = 0 in this form; nd = 0 selects an ordinary delayed branch. tf selects true (1) or false (0). No funct field. Example word: `1157693447 (0x45010007)` 0100 0101 0000 0001 0000 0000 0000 0111 For this encoded example, assume PC = 0x00400000 and label = 0x00400020. The label in the example is illustrative. Encoding checked against pinned MARS ac3d34ea65c3.
bc1f # Real	`bc1f label` Branch to label if floating-point condition flag 0 is false. This form uses the default condition code. `bc1f condition_false` COP1 / branch format · opcode 17 (0x11) · no funct opcode [6]`010001`17 (0x11)rs [5]`01000`8 (0x08)cc [3]`000`0 (0x00)nd [1]`0`0 (0x00)tf [1]`0`0 (0x00)offset [16]`branchOffset` Fields run from bit 31 on the left to bit 0 on the right. Brackets show widths. Field values use decimal followed by hexadecimal, alongside the binary bits. Immediate fields show their unsigned raw bits; signed interpretation depends on the instruction. cc = 0 in this form; nd = 0 selects an ordinary delayed branch. tf selects true (1) or false (0). No funct field. Example word: `1157627911 (0x45000007)` 0100 0101 0000 0000 0000 0000 0000 0111 For this encoded example, assume PC = 0x00400000 and label = 0x00400020. The label in the example is illustrative. Encoding checked against pinned MARS ac3d34ea65c3.
c.eq.d # Real	`c.eq.d fs, ft` Compare double-precision fs and ft. Set floating-point condition flag 0 if fs is equal to ft; clear it otherwise. In MARS, both operands name register pairs starting at even-numbered registers. `c.eq.d $f0, $f2` COP1 / compare format · opcode 17 (0x11) · funct 50 (0x32) · fmt 17 (0x11) opcode [6]`010001`17 (0x11)fmt [5]`10001`17 (0x11)ft [5]`ft`fs [5]`fs`cc [3]`000`0 (0x00)reserved [2]`00`0 (0x00)funct [6]`110010`50 (0x32) Fields run from bit 31 on the left to bit 0 on the right. Brackets show widths. Field values use decimal followed by hexadecimal, alongside the binary bits. Immediate fields show their unsigned raw bits; signed interpretation depends on the instruction. fmt describes the source representation: S = 16 (0x10), D = 17 (0x11), W = 20 (0x14). This two-operand form uses condition code cc = 0. Example word: `1176633394 (0x46220032)` 0100 0110 0010 0010 0000 0000 0011 0010 Encoding checked against pinned MARS ac3d34ea65c3.
c.lt.d # Real	`c.lt.d fs, ft` Compare double-precision fs and ft. Set floating-point condition flag 0 if fs is less than ft; clear it otherwise. In MARS, both operands name register pairs starting at even-numbered registers. `c.lt.d $f0, $f2` COP1 / compare format · opcode 17 (0x11) · funct 60 (0x3C) · fmt 17 (0x11) opcode [6]`010001`17 (0x11)fmt [5]`10001`17 (0x11)ft [5]`ft`fs [5]`fs`cc [3]`000`0 (0x00)reserved [2]`00`0 (0x00)funct [6]`111100`60 (0x3C) Fields run from bit 31 on the left to bit 0 on the right. Brackets show widths. Field values use decimal followed by hexadecimal, alongside the binary bits. Immediate fields show their unsigned raw bits; signed interpretation depends on the instruction. fmt describes the source representation: S = 16 (0x10), D = 17 (0x11), W = 20 (0x14). This two-operand form uses condition code cc = 0. Example word: `1176633404 (0x4622003C)` 0100 0110 0010 0010 0000 0000 0011 1100 Encoding checked against pinned MARS ac3d34ea65c3.
c.le.d # Real	`c.le.d fs, ft` Compare double-precision fs and ft. Set floating-point condition flag 0 if fs is less than or equal to ft; clear it otherwise. In MARS, both operands name register pairs starting at even-numbered registers. `c.le.d $f0, $f2` COP1 / compare format · opcode 17 (0x11) · funct 62 (0x3E) · fmt 17 (0x11) opcode [6]`010001`17 (0x11)fmt [5]`10001`17 (0x11)ft [5]`ft`fs [5]`fs`cc [3]`000`0 (0x00)reserved [2]`00`0 (0x00)funct [6]`111110`62 (0x3E) Fields run from bit 31 on the left to bit 0 on the right. Brackets show widths. Field values use decimal followed by hexadecimal, alongside the binary bits. Immediate fields show their unsigned raw bits; signed interpretation depends on the instruction. fmt describes the source representation: S = 16 (0x10), D = 17 (0x11), W = 20 (0x14). This two-operand form uses condition code cc = 0. Example word: `1176633406 (0x4622003E)` 0100 0110 0010 0010 0000 0000 0011 1110 Encoding checked against pinned MARS ac3d34ea65c3.

Common pitfalls

The u suffix does not always mean unsigned operands

For addu / subu / addiu, the key distinction is the absence of a signed-overflow exception. addiu still sign-extends its immediate, so addiu $sp,$sp,-16 is valid. In contrast, sltu / divu / multu really do interpret their operands as unsigned.

li    $t1, -1              # Bit pattern: 0xffffffff
slt   $t0, $t1, $zero     # -1 < 0: result 1
sltu  $t0, $t1, $zero     # 4294967295 < 0: result 0
sltiu $t0, $zero, -1      # Immediate becomes 0xffffffff: result 1

Sign extension, zero extension and right shifts

A 16-bit field does not imply the same immediate range for every instruction. addi/addiu/slti/sltiu and memory offsets use sign extension; andi/ori/xori use zero extension. Loading byte 0xff with lb produces 0xffffffff; lbu produces 0x000000ff.

# If t1 = 0x80000000:
srl $t0, $t1, 1          # 0x40000000: fill with zeroes
sra $t0, $t1, 1          # 0xc0000000: replicate the sign bit

Addresses are not contents; offsets are bytes

la $t0,array obtains an address; lw $t1,0($t0) reads the contents. Element i of a 32-bit integer array lives at base + 4*i. Memory offsets are always measured in bytes. Endianness changes how multibyte values are arranged in memory, not the direction of register shifts.

Multiplication and division boundaries

Two-operand div s,t writes HI/LO; three-operand div d,s,t is a common pseudo-instruction. Check division by zero and INT_MIN / -1 explicitly instead of depending on results across environments. A later multiply or divide may overwrite HI/LO before you read them. The low 32-bit result of mul is not an automatically checked mathematical integer.

Delay slots depend on execution mode

On classic MIPS with delay slots, the instruction immediately after an ordinary branch or jump still executes. Standard MARS 4.5 disables delayed branching by default and does not insert nop instructions automatically. With delay slots enabled, a call links to PC+8; with them disabled, MARS saves a return location appropriate for execution without a delay slot. Check the settings and implementation of course-specific forks. The examples explicitly use nop slots and avoid placing multi-instruction pseudo-operations in them.

Settings: MARS settings documentation. Instruction details: MARS basic-instruction implementation; MARS pseudo-instruction expansion table.

Machine-word tools

These tools cover the real instruction forms in this guide. All calculations run locally. They do not assemble pseudo-instructions, link symbols, execute code or validate a whole program.

Build from fields

Instruction

Inspect a machine word

Hexadecimal word or 32 binary bitsInstruction address (PC)

Calculate branch and jump targets

Instruction address (PC)Target byte address

Compare instructions

Select two mnemonics here, or use Compare on any two instruction entries.

First instructionSecond instruction

Machine-code formats

Classic MIPS32 instructions are 32 bits long. R, I and J describe field layouts, not an exhaustive semantic classification.

R: opcode[6] rs[5] rt[5] rd[5] shamt[5] funct[6]
I: opcode[6] rs[5] rt[5] immediate[16]
J: opcode[6] target[26]

Example	Fields and encoding
`addu $t0,$t1,$t2`	op=0 (0x00), rs=9 (0x09), rt=10 (0x0A), rd=8 (0x08), shamt=0 (0x00), funct=33 (0x21) → `19546145 (0x012A4021)`
`addiu $t0,$zero,-1`	op=9 (0x09), rs=0 (0x00), rt=8 (0x08), imm=65535 (0xFFFF) → `604569599 (0x2408FFFF)`
`lw $t0,4($sp)`	op=35 (0x23), rs=29 (0x1D), rt=8 (0x08), imm=4 (0x0004) → `2410151940 (0x8FA80004)`

Branch and jump targets

Ordinary conditional branch target: (PC+4) + (sign_extend(imm16) << 2). The encoded range relative to PC+4 is −131072…+131068 bytes, in four-byte steps. Write a label in assembly; the assembler calculates the offset.

j/jal target: {(PC+4)[31:28], target26, 00}. This pseudo-direct encoding selects a location in a 256 MiB region. Use jr/jalr for a target held in a register. See MARS basic-instruction implementation.

Typical pseudo-instruction expansions

move $t0, $t1             # e.g. addu $t0,$t1,$zero
not  $t0, $t1             # e.g. nor  $t0,$t1,$zero
li   $t0, 0x12345678      # One possible expansion:
     lui $t0, 0x1234
     ori $t0, $t0, 0x5678
blt  $t0, $t1, less       # One possible expansion:
     slt $at, $t0, $t1
     bne $at, $zero, less
     nop                  # Explicit branch delay slot

These are equivalent implementations, not a guarantee of a particular assembler's output. la depends on addresses, relocations and the toolchain; it is not universally a fixed lui+ori sequence. For exact MARS expansions, see MARS pseudo-instruction expansion table.

Functions and the stack

A function that calls another function must protect its own return address. A callee that modifies $s0–$s7 must restore them. Temporary, argument and return-value registers may change across a call.

# Structure only: helper must be implemented separately.
# Reserve 16 bytes for outgoing arguments, following an o32-style convention.
# A 24-byte frame preserves 8-byte alignment.
f:
    addiu $sp, $sp, -24
    sw    $ra, 20($sp)
    sw    $s0, 16($sp)
    move  $s0, $a0
    jal   helper
    nop
    # Use helper's result here; s0 still holds this function's saved value.
    lw    $s0, 16($sp)
    lw    $ra, 20($sp)
    addiu $sp, $sp, 24
    jr    $ra
    nop

Argument areas, stack alignment and floating-point arguments must follow your actual ABI. The fragment above demonstrates structure; a complete program follows below.

Common MARS system calls

Load the service number into $v0, set the arguments, execute syscall, then read the result. This table describes MARS simulation services, not Linux MIPS system calls.

$v0	Service, arguments and result
`1 / 4 / 11`	Print integer / null-terminated string / character. $a0 holds the integer / string address / character low byte.
`5 / 12`	Read an integer / character; result in $v0. Save it before loading the next service number.
`8`	Read a string: $a0 = buffer address, $a1 = capacity n. For n ≥ 2, read at most n−1 characters and append a null byte. A newline may be retained.
`9 / 10`	Allocate heap memory / exit. For service 9: $a0 = byte count; $v0 receives the address.
`2 / 3; 6 / 7`	Print float / double from $f12; read float / double into $f0.
`13 / 14 / 15 / 16`	Open / read / write / close a file; consult the original documentation for flags, arguments and results.
`34 / 35 / 36`	MARS extensions: print $a0 in hexadecimal / binary / unsigned decimal.

Service definitions: MARS syscall documentation. Custom MARS versions may add services.

Assembler directives are not CPU instructions

Directive	Purpose
`.text / .data`	Select the code / data section.
`.globl main`	Declare main as a global symbol; entry-point selection also depends on the execution environment.
`.word / .half / .byte`	Define 4-byte / 2-byte / 1-byte integer data.
`.float / .double`	Define single-precision / double-precision data.
`.ascii / .asciiz`	Define a string; .asciiz adds a terminating null byte.
`.space n`	Reserve n bytes; do not assume initial contents across toolchains.
`.align n`	In MARS, align to a 2ⁿ-byte boundary; .align 2 means four-byte alignment. Other assemblers may differ.

Environment reference: MARS help.

Complete example: sum an array and print 15

For standard MARS 4.5 with pseudo-instructions enabled. Explicit nop slots allow this example to work with delayed branching either enabled or disabled. It requires no input and uses only integer output, character output and exit services.

# MARS 4.5: sums 1 + 2 + 3 + 4 + 5 and prints 15.
# Pseudo instructions enabled. nop slots work with delayed branching on or off.
.data
.align 2
array: .word 1, 2, 3, 4, 5
.text
.globl main
main:
    la    $a0, array
    li    $a1, 5
    jal   sum_array
    nop
    move  $a0, $v0
    li    $v0, 1
    syscall
    li    $a0, 10
    li    $v0, 11
    syscall
    li    $v0, 10
    syscall

# Input: a0 = array address, a1 = nonnegative length.
# Output: v0 = sum modulo 2^32. Clobbers t0, t1, t2.
sum_array:
    move  $v0, $zero
    move  $t0, $a0
    move  $t1, $a1
loop:
    beq   $t1, $zero, done
    nop
    lw    $t2, 0($t0)
    addu  $v0, $v0, $t2
    addiu $t0, $t0, 4
    addiu $t1, $t1, -1
    j     loop
    nop
done:
    jr    $ra
    nop

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